Nitrogen93 SMARC

Scope

This document describes key hardware aspects of Ezurio’s Nitrogen93 SMARC system-on-module which is based on the i.MX 93 processor family and the Sona IF573 Wi-Fi/BT combo radio. Data in this document is drawn from several sources and includes information found in the documentation for NXP’s i.MX 93 and our Sona IF573.

Introduction

Overview

This document describes key hardware aspects of the Nitrogen93 SMARC. This document is intended to assist device manufacturers and related parties with the integration of this radio into their host devices. Data in this document is drawn from several sources. For full documentation on the Nitrogen93 SMARC, visit:

https://www.ezurio.com/nitrogen93-smarc

General Description

The Nitrogen93 SMARC is an integrated platform solution with the NXP I.MX 93 processor that integrates a dual Arm® Cortex®-A55 cluster operating up to 1.7 GHz, a 250 MHz Arm Cortex-M33 and pre-certified tri-band 8 02.11 a/b/g/n/ac/ax WLAN plus dual-mode Bluetooth® 5.4 L ow Energy module.

The Arm® Cortex®-A55 cores bring best-in-class performance and energy efficiency to Linux-based edge applications and the Arm Cortex-M33 processor can perform time-critical real-time compute and control.

The processor also embeds the Arm® Ethos™-U65 microNPU, a dedicated neural processing unit (NPU) which delivers a combination of performance and efficiency with an optimized footprint that enables developers to create high-performance, cost-effective and energy-efficient ML applications. Also, the built-in Arm Cortex M33 in conjunction with the NPU can be used for low-power wake-word detection.

Additionally, it offers the latest high-speed interfaces for connectivity and fast data transfer with 2x USB 2.0, 3x SD/SDIO 3.01, 2x Gbit Ethernet with EEE, AVB, IEEE 1588, in addition to 2x CAN-FD interfaces. The memory interfaces supported are 16-bit LPDDR4X and eMMC 5.1.

The module also includes a 2-lane MIPI-CSI camera interface capable of supporting 1080p60 resolution as well as a 4-lane MIPI-DSI output capable of supporting 1080p60 resolution or a 4-lane LVDS one supporting 720p60 for multimedia applications.

The i.MX 93 family implements security via NXP’s EdgeLock® secure enclave, a preconfigured, self-managed and autonomous security subsystem. EdgeLock eases the complexity of implementing robust, device-wide security intelligence for IoT applications through autonomous management of critical security functions, such as root of trust, run-time attestation, trust provisioning, secure boot, key management and cryptographic services while also simplifying the path to industry-standard security certifications.

The Nitrogen93 SMARC includes the Sona IF573 which is pre-calibrated and integrates the complete transmit/receive RF paths including bandpass filter, diplexer, switches, reference crystal oscillator, and power management units (PMU). Three RF connectors (MHF4) on the module provide the most flexibility for antenna selection, installation and performance. Two ports for WLAN and one dedicated for Bluetooth. Several high-performance antennas are certified with the Sona IF573 onboard the Nitrogen93 SMARC.

The Nitrogen93 SMARC has several product SKUs providing different eMMC and LPDDR4 memory configurations, see Ordering Information section.

This datasheet is subject to change. Please contact Ezurio for further information.

Errata

ERRATA1: Addition of Pull-Up Resistors for i2C Communication

Issue: In the current design of IMX93_SMARC REV 20, pull-up resistors were not included on the I2C_GP(S48,S49).

Impact: This omission affects the reliability of I2C communication, particularly at higher speeds.

Resolution: To address this issue, it is recommended to add pull-up resistors to the I2C_GP on the product's carrier board. Pull-up resistors should be of appropriate value to ensure proper signal integrity. The recommended value for pull-up resistors typically falls in the range of 2.2kΩ to 10kΩ, depending on factors such as bus capacitance and desired speed.

Action: Future revisions of the product should include pull-up resistors on the I2C lines as per the recommended values mentioned above. 

Specification Summary

Processor / SoC / Chipset

Radio Performance

Interfaces

Power

Mechanical

Software

Environmental

Certifications

Development

Warranty

Functional Descriptions

Power-Up Sequence and Timing

Boot Mode

The Nitrogen93 SMARC module contains a switch (SW1) connected to BOOT_MODE0 thus allowing to switch from internal fuses boot (eMMC by default) to USB serial downloader.

The other boot mode signals (BOOT_MODE[1-3]) are not exposed to the carrier as used for different functions (UART/I2S). But a BOM change can select a custom boot mode (see resistors R128 to R135).

This allows more combinations as shown in the following table.

Boot mode combinations

Hardware Architecture

Block Diagrams

The figure below shows the block diagram of the Nitrogen93 SMARC which contains the NXP i.MX 93 processor, PMIC (PCA9451A) and the Sona IF573 Wi-Fi/BT combo.

Detailed connections between the IF573 and the i.MX 93 are detailed in the Table below.

Sona IF573 to i.MX 93 Connections

Pin-Out and Pinmux Table

The following tables list the pin multiplexing (PIN-MUX) of the Nitrogen93 SMARC.

PO = Power Output, PI = Power Input, DI = Digital Input, DO = Digital Output, DIO = Bi-directional Digital Port, GND = Ground

NXP process has configurable internal Pull-up (PU) and pull-down (PD) resistor whose values are listed below. During a reset condition, the PU and PD state are pre-defined and cannot be changed.

Resistor characteristics

Pin configuration for the i.MX is achieved using a suite of evaluation and configuration tools that assists users from initial evaluation to production software development. Users can download the tool from the NXP website: https://www.nxp.com/design/designs/config-tools-for-i-mx-applications-processors:CONFIG-TOOLS-IMX?tab=Design_Tools_Tab

Pinout table for Nitrogen93 SMARC edge connector (J2)

Mechanical Drawings

Module dimensions of the Nitrogen93 SMARC are 82 x 50 mm. Detail drawings are shown below.

Pin Definitions & Functionality (and PIN-MUX, if applicable)

Electrical Characteristics

Absolute Maximum Ratings

The following tables summarizes the absolute maximum ratings for the Nitrogen93 SMARC product series. Absolute maximum ratings are those values beyond which damage to the device can occur. Functional operation under these conditions, or at any other condition beyond those indicated in the operational sections of this document, is not recommended.

Absolute maximum ratings

Recommended Operating Conditions

The following tables summarizes the recommended operating conditions for the Nitrogen93 SMARC product series.

Recommended Operating Conditions

DC Electrical Characteristics / Current Consumption

Several power saving modes are available and are listed in the following table.

Typical current consumption

Power Management & Consumption

DC Power Tree

The Nitrogen93 SMARC requires a primary 5V power supply (VSYS) input. This supply is the main power domain to the on-module NXP PCA9451A power management IC (PMIC), which generates all required supply voltages for the module components.

Power Modes

NXP PCA9451A has eight power modes: OFF, READY, SNVS, RUN, STANDBY, PWRDN, PWRUP and FAULT_SD. Below figure shows the state transition diagram showing the conditions to enter and exit each state.

• OFF mode:
  PMIC will enter OFF mode from any state when the main power source VSYS_5V falls below V_{sys_POR} threshold (2.2 to 2.6V; typ.=2.4V). All regulators are OFF and all registers are reset in this mode.
• READY Mode:
  PMIC enters READY mode when VSYSY_5V is higher than V_{sys_POR}. The internal LDO VINT is enabled and loads the MTP data to registers. Once the MTP data loading is complete, the state machine is ready to transition to SNVS mode.
• SNVS Mode:
  PMIC will enter SNVS (Secure Non-Volatile Storage mode) when VSYS_5V exceeds the V_{sys_UVLO} threshold. LDO1 is powered up and the 32.778KHz buffer starts running. RTC_RESET_B is pulled high after both LDO1 and LDO2 voltage come up.
  Note: PMIC_ON_REQ input is masked until RTC_RESET_B is released. PMIC will start power up sequence if PMIC_ON_REQ is asserted high in this mode.
• PWRUP Mode:
  After RTC_RESET_B is released in SNVS mode, the PMIC starts power up with a pre-defined sequence with PMIC_ON_REQ asserted high.
  During PWRUP mode, PMIC_STBY_REQ signal is masked until POR_B is released. The PWRUP mode ends up releasing POR_B and the PMIC is transitioned to RUN mode.
• PWRDN Mode:
  When PMIC_ON_REQ is low in RUN or STANDBY mode, PMIC enters PWRDN mode, where it starts with pulling down POR_B. and then by turning off each power rail before transitioning to SNVS mode.
• RUN Mode:
  PMIC operates in RUN mode when PMIC_ON_REQ is driven high and PMIC_STBY_REQ is driven low. When PMIC_STBY_REQ is asserted high in this mode, it is transitioned to STANDBY mode. PMIC_ON_REQ is asserted low, it moves to PWRDN mode.
• STANDBY Mode:
  PMIC is transitioned to STANDBY mode from RUN mode when both PMIC_ON_REQ and PMIC_STBY_REQ are driven low.  If PMIC_ON_REQ is asserted low, then it is transitioned to PWRDN mode. If PMIC_STBY_REQ is driven low, it is transitioned to RUN mode.

• FAULT_SD Mode:
  PCA9451A has three kinds of Fault sources.

  • Thermal shutdown: Transition to SNVS mode or READY mode after Fault_SD mode.
    When junction temperature reaches 150℃, it enters FAULT_SD mode after 120μs where regulators are tuned off simultaneously. It stays at FAULT_SD mode until the junction temperature fall below 150℃, then move to READY state if any of LDO1 and LDO2 is fault is triggered. And it will move to SNVS mode if either LDO1 or LDO2 fault is triggered.
  • Voltage regulator fault during power up: Transition to READY mode after FAULT_SD mode.
    Any POK of voltage regulator doesn’t come up within 10ms after regulator is enabled during power up sequence, it stops power-up sequence and then moves into FAULT_SD mode where all regulators are turned off.
  • Voltage regulator fault in STBY and RUN MODE: Move to FAULT_SD mode in 100ms after fault is detected. Transition to SNVS mode or READY mode after FAULT_SD mode.

Environmental and Reliability

Environmental Requirements

Required Storage Conditions

• Prior to Opening the Dry Packing:
  The following are required storage conditions prior to opening the dry packing:

  • Normal temperature: 5~40℃
  • Normal humidity: 80% (Relative humidity) or less
  • Storage period: One year or less

Regulatory, Qualification & Certifications

Regulatory Approvals

Radio certifications for SOMs with wireless options are held under the specific wireless module listings:

Ordering Information

Legacy - Revision History

Additional Information

Please contact your local sales representative or our support team for further assistance:

Note:   Information contained in this document is subject to change.

 Ezurio’s products are subject to standard Terms & Conditions.